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integrated synthesizer and vco adf4360-3 rev. b in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures output freq ue ncy range: 160 0 mhz to 1950 mhz divid e -by- 2 o u tput 3.0 v to 3.6 v p o wer supply 1.8 v logic compatibility integer-n synt hesizer programmable dua l -modul us prescaler 8/9, 1 6 /17, 32/33 programmable output power level 3-wire seri al in terface analo g and d i gital lo ck de tect hardware and software power-down mode applic a t io ns wireless han d s e ts (dect, gsm , pcs, dcs, wcdma) test eq uipmen t wireless lans catv equipment gener a l description the ad f4360-3 is a f u l l y in t e g r a t e d in t e ger - n s y n t h e sizer an d v o l t a g e con t r o l l ed os cil l a t o r ( v co). th e ad f4 360-3 is desig n e d f o r a cen t er f r eq uen c y o f 1750 mh z. i n addi tion, th er e is a divide -b y-2 o p t i o n a v a i lab l e , w h er eb y t h e us er g e ts a n rf o u t - p u t o f betw een 800 mh z and 9 75 mh z. c o n t ro l of a l l t h e on - c h i p re g i st e r s i s t h rou g h a s i m p l e 3 - w i re in t e r f ace . the de v i ce o p er a t es wi t h a p o w e r s u p p l y ra n g in g f r o m 3.0 v to 3.6 v and can b e p o w e r e d do w n w h e n n o t i n us e. func ti on a l bl ock di a g r a m muxout cp v vco ref in clk data le av dd dv dd ce agnd dgnd cpgnd r set v tune c c c n rf out a rf out b vco core phase comparator mute divsel = 2 divsel = 1 n = (bp + a) load load charge pump output stage m u l t i pl exer integer register 13-bit b counter 14-bit r counter 24-bit function latch 24-bit data register 5-bit a counter prescaler p/p+1 multiplexer lock detect 2 a d f43 60-3 04437-001 fi g u r e 1 .
adf4360-3 rev. b | page 2 of 24 table of contents specifications ..................................................................................... 3 timing characteristics ..................................................................... 5 absolute maximum ratings ............................................................ 6 transistor c ount ........................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 circuit description ........................................................................... 9 reference input section ............................................................... 9 prescaler (p/p + 1) ........................................................................ 9 a and b counters ......................................................................... 9 r counter ...................................................................................... 9 pfd and charge pump ................................................................ 9 muxout and lock detect ...................................................... 10 input shift register ..................................................................... 10 vco ............................................................................................. 10 output stage ................................................................................ 11 latch structure ........................................................................... 12 power-up ..................................................................................... 16 control latch .............................................................................. 18 n counter latch ......................................................................... 19 r counter latch ......................................................................... 19 applications ..................................................................................... 20 direct conversion modulator .................................................. 20 fixed frequency lo ................................................................... 21 interfacing ................................................................................... 21 pcb design guidelines for chip scale package ........................... 22 output matching ........................................................................ 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 12/04rev. a to rev. b updated format................................................................ universal changes to specifications ............................................................... 3 changes to timing characteristics ............................................... 5 changes to the power-up section............................................... 16 added table 10 .............................................................................. 16 added figure 16............................................................................. 16 changes to ordering guide ......................................................... 23 updated outline dimensions ...................................................... 23 4/04data sheet changed from rev. 0 to rev. a updated format................................................................ universal changes to figure 5 and figure 6 captions ................................. 8 changes to table 6......................................................................... 12 changes to table 7......................................................................... 13 changes to table 9......................................................................... 15 11/03revision 0: initial version
adf4360-3 rev. b | page 3 of 24 specifications 1 av dd = dv dd = v vco = 3.3 v 10%; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted. table 1. parameter b version unit conditions/comments ref in characteristics ref in input frequency 10/250 mhz min/max for f < 10 mhz, use a dc-coupled cmos-compatible square wave, slew rate > 21 v/s. ref in input sensitivity 0.7/av dd p-p min/max ac-coupled. 0 to av dd v max cmos compatible. ref in input capacitance 5.0 pf max ref in input current 100 a max phase detector phase detector frequency 2 8 mhz max charge pump i cp sink/source 3 with r set = 4.7 k?. high value 2.5 ma typ low value 0.312 ma typ r set range 2.7/10 k? i cp 3-state leakage current 0.2 na typ sink and source current matching 2 % typ 1.25 v v cp 2.5 v. i cp vs. v cp 1.5 % typ 1.25 v v cp 2.5 v. i cp vs. temperature 2 % typ v cp = 2.0 v. logic inputs v inh , input high voltage 1.5 v min v inl , input low voltage 0.6 v max i inh /i inl , input current 1 a max c in , input capacitance 3.0 pf max logic outputs v oh , output high voltage dv dd C 0.4 v min cmos output chosen. i oh , output high current 500 a max v ol , output low voltage 0.4 v max i ol = 500 a. power supplies av dd 3.0/3.6 v min/v max dv dd av dd v vco av dd ai dd 4 10 ma typ di dd 4 2.5 ma typ i vco 4 , 5 24.0 ma typ i core = 15 ma. i rfout 4 3.5C11.0 ma typ rf output stage is programmable. low power sleep mode 4 7 a typ rf output characteristics 5 vco output frequency 1600/1950 mhz min/max i core = 15 ma. vco sensitivity 45 mhz/v typ lock time 6 400 s typ to within 10 hz of final frequency. frequency pushing, (open loop) 6 mhz/v typ frequency pulling, (open loop) 15 khz typ into 2.00 vswr load. harmonic content (second) ?19 dbc typ harmonic content (third) ?37 dbc typ output power 5 , 7 ?12/?3 dbm typ programmable in 3 db steps. see table 7. output power variation 3 db typ for tuned loads, see output matching section. vco tuning range 1.25/2.5 v min/max
adf4360-3 rev. b | page 4 of 24 parameter b version unit conditions/comments noise characteristics 1 , 5 vco phase-noise performance 8 ?110 dbc/hz typ @ 100 kh z offset from carrier. ?133 dbc/hz typ @ 1 mhz offset from carrier. ?141 dbc/hz typ @ 3 mhz offset from carrier. ?146 dbc/hz typ @ 10 mhz offset from carrier. synthesizer phase-noise floor 9 ?172 dbc/hz typ @ 25 khz pfd frequency. ?163 dbc/hz typ @ 200 khz pfd frequency. ?147 dbc/hz typ @ 8 mhz pfd frequency. in-band phase noise 10 , 11 ?85 dbc/hz typ @ 1 khz offset from carrier. rms integrated phase error 12 0.57 degrees typ 100 hz to 100 khz. spurious signals due to pfd frequency 11, 13 ?65 dbc typ level of unlocked signal with mtld enabled ?41 dbm typ 1 operating temperature range is C40c to +85c. 2 guaranteed by design. sample tested to ensure compliance. 3 i cp is internally modified to maintain constant loop gain over the frequency range. 4 t a = 25c; av dd = dv dd = v vco = 3.3 v; p = 32. 5 these characteristics are guarant eed for vco core power = 15 ma. 6 jumping from 1.6 ghz to 1.95 ghz. pfd fr equency = 200 khz; loop bandwidth = 10 khz. 7 using 50 ? resistors to v vco , into a 50 ? load. for tuned loads, see the output m section. atching 8 the noise of the vco is meas ured in open-loop conditions. 9 the synthesizer phase -noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 20 log n (where n is the n divider value). 10 the phase noise is measured with the eval-adf4360- xeb1 evaluation board an d the hp8562e spectrum analyzer. the spectrum analyz er provides the ref in for the synthesizer; offset frequency = 1 khz. 11 f refin = 10 mhz; f pfd = 200 khz; n = 9,000; loop b/w = 10 khz. 12 f refin = 10 mhz; f pfd = 1 mhz; n = 1,800; loop b/w = 25 khz. 13 the spurious signals are meas ured with the eval-adf4360- xeb1 evaluation board and the hp8562e spectrum analyzer. the spectrum analyzer provides the ref in for the synthesizer; f refout = 10 mhz @ 0 dbm.
adf4360-3 r e v. b | pa ge 5 o f 2 4 timing characteristics 1 av dd = d v dd = v vc o = 3.3 v 10%; a g nd = d g nd = 0 v ; 1. 8 v a nd 3 v log i c lev e l s us ed; t a = t min to t max , u n l e s s o t h e r w i s e n o t e d . table 2. parameter limit at t min to t ma x (b version ) unit test condition s /comments t 1 20 ns min le setup time t 2 10 ns min data to clock setup time t 3 10 ns min data to clock hold time t 4 25 ns min clock high duration t 5 25 ns min clock low duration t 6 10 ns min clock to le set u p time t 7 20 ns min le pulse width 1 see the section for the r e commended powe r - up p r ocedur e for this device. pow e r-up cloc k data le le db23 (msb) db22 db2 db1 (lsb) (control bit c2) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 04437-002 f i g u re 2. ti ming d i ag r a m
adf4360-3 r e v. b | pa ge 6 o f 2 4 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 3. p a r a m e t e r r a t i n g av dd to gnd 1 ?0.3 v to +3.9 v av dd to dv dd ?0.3 v to +0.3 v v vco to gnd ?0.3 v to +3.9 v v vco to av dd ?0.3 v to +0.3 v digital i/o voltage to gnd ?0.3 v to v dd + 0.3 v analog i/o voltage to gnd ?0.3 v to v dd + 0.3 v ref in to gnd ?0.3 v to v dd + 0.3 v operating tem p erature range maximum junction temperature 150c csp ja thermal impedance (paddl e sol d ered) 50c/ w (paddl e not sol d ered) 88c/ w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c 1 gnd = agnd = dgnd = 0 v. s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t - i n g on ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e m a xi- m u m r a t i n g condi t i on s fo r ex ten d e d p e r i o d s m a y a f fe c t de vice rel i a b i l it y . this de vice is a hig h p e r f o r ma n c e rf in t e g r a t e d cir c ui t wi t h an es d ra tin g o f <1 kv and i t is e s d s e n s i t i v e . p r o p er p r eca u tio n s s h o u ld b e ta k e n f o r ha n d lin g and as s e m b l y . transis t o r count 12543 (cm o s) a nd 700 (b i p ol ar). esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge without detection. although this product features proprie - tary esd protect i on circuitry, permanent damag e may o ccur on devices subje c ted to high energy electrostatic discharges. ther efore, prop er esd precautions a r e reco mmende d to avoid performance degradation or lo ss of functionality.
adf4360-3 r e v. b | pa ge 7 o f 2 4 pin conf iguration and fu nction descriptions adf4360-3 top view (not to scale) cpgnd 1 av dd 2 agnd 3 rf out a 4 rf out b 5 v vco 6 data 18 clk 17 ref in 16 dgnd 15 c n 14 r set 13 v tune 7 agnd 8 agnd 9 agnd 10 agnd 11 c c 12 cp 24 ce 23 agnd 22 dv dd 21 mux o u t 20 le 19 04437-003 pin 1 identifier f i gure 3. pin config ur ation ta ble 4. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic function 1 cpgnd charge pump ground. this is the ground return path for the charge pump. 2 a v dd analog power s u pply. this rang es from 3.0 v to 3.6 v. decouplin g capacitor s to the anal og ground plane should be pl ace d as close a s po s s ible to this p i n. av dd must have the same value as dv dd . 3, 8 to 11, 22 agnd analog ground. this is th e ground return path of the presca ler and vco. 4 r f ou t a vco output. the output level is programma ble f r om C3 dbm to ?12 dbm. see th e output matchi ng section for a description of the various output stages. 5 r f ou t b vco compleme ntary output. the output level is prog ramm able from ?3 dbm to ?12 dbm. see output matching section for a description of the variou s output stages. 6 v vco power supply for the vco. this ranges from 3.0 v to 3.6 v. decoupling capa citors to the analog ground plane should be pl ace d as close a s po s s ible to this p i n. v vco must have the same va lue a s av dd . 7 v tu ne control input to the vco. this volt age determines the output fr eq uency an d is derived from filtering the cp output voltage. 1 2 c c internal compe n sation node. this pin must be decoupled to ground with a 10 nf capacitor. 1 3 r set connecting a re sistor betwe e n this pin a n d cp gnd sets the maxi mum charge pump output curr ent for the synthesizer. the nomina l voltag e potential at th e r set pin is 0.6 v. t h e relationsh i p between i cp an d r set is set cpmax r i = with r set = 4.7 k?, i cpma x = 2.5 ma. 1 4 c n internal compensation node. this pin must be decoupled to v vco with a 10 f capacitor. 15 dgnd digital ground. 1 6 r e f in reference input. t h is is a cmos in put with a nomin a l th reshold o f v dd /2 an d a dc equi valent inp u t res i stance of 100 k?. s ee fig u re 1 0 . th is i n put can be driven fro m a tt l or cmos crystal oscilla tor or it ca n be ac-co u ple d . 1 7 c l k se ria l cl oc k in put. th is s e ria l c l oc k is used to clock in the seri al data to the registers. the data is latched into the 24-bit shift register on the clk rising edge. this input is a hig h impedance c m os input. 1 8 d a t a serial data inpu t. the serial data is loaded msb first with the two lsbs be ing the c o ntrol bits. this input is a high impedance cmos input. 1 9 l e load enable, c m os input. when le goes high, the data stored in the shift registers is lo aded into one of the four latches, and the relevant latch is selected using the control bits. 2 0 m u x o u t t h is multiplexer output allows e i ther th e lock de tect, the scaled rf, or th e scaled reference frequ e ncy to be accessed extern ally. 2 1 d v dd digital power s u pply. this rang es from 3.0 v to 3.6 v. decouplin g capacitor s to the digital ground plane should be pl ace d as close a s po s s ible to this p i n. dv dd must have the same value as av dd . 2 3 c e chip enab le. a l o gic low on this pin po wers d o w n th e device an d puts the charge pump into three-state mode. taking the pin high po we rs up the device depending on the status of the power-do w n bit s . 2 4 c p charge pump output. when en abled, this pr ovi d es i cp to the e x ternal l oop fi lter, which in turn drives the internal vco.
adf4360-3 r e v. b | pa ge 8 o f 2 4 typical perf orm ance cha r acte ristics 04437-004 ?150 ?160 ?170 ?140 ?130 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?4 0 ?5 0 ?6 0 ?3 0 ?2 0 ?1 0 0 1k 10m 1m 100k 10k frequency offset (hz) 4 3 2 1 outp ut p o we r (db) f i gure 4. o p en-l o o p vc o p h ase n o ise 04437-005 100 10m 1m 100k 10k 1k frequency offset (hz) outp ut p o we r (db) ?145 ?150 ?140 ?135 ?130 ?125 ?120 ?115 ?110 ?105 ?9 0 ?9 5 ?100 ?8 5 ?8 0 ?7 5 ?7 0 f i g u re 5. v c o p h as e n o is e , 18 00 m h z , 20 0 k h z pfd , 1 0 k h z l oop band widt h 04437-006 ?145 ?150 ?140 ?135 ?130 ?125 ?120 ?115 ?110 ?105 ?9 0 ?9 5 ?100 ?8 5 ?8 0 ?7 5 ?7 0 100 10m 1m 100k 10k 1k frequency offset (hz) outp ut p o we r (db) f i g u re 6. v c o p h as e n o is e , 90 0 m h z, d i v i d e -by-2 e n ab le d , 2 00 k h z pfd , 10 k h z l o op b a ndw i d t h 04437-007 outp ut p o w e r (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?2khz ? 1khz 1800mhz 1khz 2khz ?86.0dbc/hz v dd = 3v, v vco = +3v i cp = 2.5ma pfd frequency = 200khz loop bandwidth = 10khz res. bandwidth = 30hz video bandwidth = 30hz sweep = 1.9 seconds averages = 10 f i g u re 7. cl os e - in phas e n o is e at 1 8 0 0 m h z ( 2 0 0 k h z ch a nnel spa c ing ) 04437-008 outp ut p o w e r (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ? 200khz ?100khz 1800mhz 100khz 200khz ? 72.3dbc v dd = +3v, v vco = +3v i cp = 2.5ma pfd frequency = 200khz loop bandwidth = 10khz res. bandwidth = 3khz video bandwidth = 3khz sweep = 140ms averages = 100 f i gure 8. refe r e n c e spurs at 18 0 0 mh z (200 kh z ch anne l s p ac ing , 10 khz l o op bandw i dth) 04437-009 outp ut p o w e r (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ? 1mhz ? 0.5mhz 1800mhz 0.5mhz 1mhz ?73.8dbc/hz v dd = +3v, v vco = +3v i cp = 2.5ma pfd frequency = 1mhz loop bandwidth = 25khz res. bandwidth = 30khz video bandwidth = 30khz sweep = 50ms averages = 100 f i gu r e 9 . re fer e nc e s p u r s a t 1 800 mh z (1 mh z ch anne l sp ac ing , 25 khz l oop bandw i dth)
adf4360-3 r e v. b | pa ge 9 o f 2 4 circuit description reference input section the r e fer e n c e i n p u t s t a g e is sho w n i n f i gur e 1 0 . sw1 an d s w 2 a r e n o r m al ly clos e d s w i t ch es. sw3 is n o r m al ly o p en. w h e n p o w e r - do w n is i n i t ia te d , sw3 is clo s e d , a nd s w 1 a nd sw2 a r e o p ene d . this ens u r e s t h a t t h er e is n o lo adin g o f t h e ref in pi n on p o we r - d o w n . 04437-010 buffer to r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down control f i gure 10. r e ference input stag e prescaler (p/p + 1) the d u al- m o d u l us p r es caler (p/p + 1), alo n g wi t h t h e a and b co un t e rs, ena b le s t h e l a rg e divisi o n ra t i o , n , t o b e r e a l i z e d (n = b p + a). th e d u al - m o d u l us p r es caler , o p era t in g a t cml lev e ls , tak e s th e c l oc k f r o m th e v c o a n d d i v i de s i t d o wn t o a ma na g e ab le f r e q uen c y fo r t h e cmos a and b co un t e rs. th e p r es caler is p r og ra mma b l e . i t c a n be s et in s o f t wa r e t o 8/9, 16/17, o r 32/33 a nd is bas e d on a sy n c hr on o u s 4/5 co r e . th er e is a m i nim u m di vid e ra tio pos s ib le f o r f u ll y co n t iguo us o u t p u t f r eq ue n c i e s ; th is m i n i m u m i s de t e rm in ed b y p , th e p r e s cale r va l u e, a nd is g i ven b y ( p 2 ? p). a and b counters the a an d b c m os co un t e rs c o m b i n e w i t h t h e d u a l - m o d u l us p r escaler t o allo w a wid e ran g e d i visio n ra t i o in th e pll f e e d - b a ck co u n t e r . th e co u n t e rs a r e s p e c if ie d t o w o rk w h e n t h e p r e- s c aler o u t p u t is 300 mh z o r les s . th us, wi th a v c o f r eq uen c y of 2.5 gh z, a p r es caler val u e o f 16/17 is valid , b u t a val u e o f 8/9 is not v a l i d. pulse swallow function the a an d b coun t e rs, in con j u n c t ion wi t h the d u al -m o d u l us p r es caler , mak e i t p o s s ib le t o g e n e ra t e o u t p u t f r eq uen c ies tha t a r e s p a c ed o n l y b y th e r e f e r e n c e f r eq ue n c y d i v i d e d b y r . th e v c o f r eq uen c y eq ua ti o n i s () r f a b p f refin vco / ] + [ = w h er e: f vc o i s th e o u t p u t f r eq ue n c y o f th e v c o . p is t h e p r es et m o d u l u s o f t h e d u al - m o d u l us p r es caler (8/9, 16/17, a nd s o on). b is t h e p r es et di vide ra t i o o f t h e b i na r y 13-b i t co un t e r (3 t o 8191). a i s th e p r e s e t d i v i d e ra ti o o f th e b i n a r y 5- b i t s w all o w c o un t e r ( 0 t o 31 ) . f refin is t h e ext e r n al r e fer e n c e f r e q uen c y os ci l l a t or . n = bp + a to pfd from vco n divider modulus control load load 13-bit b counter 5-bit a counter prescaler p/p+1 04437-011 f i gure 11. a and b counters r counter t h e 14-b i t r co un t e r allo w s th e i n p u t r e f e r e n c e f r eq ue n c y t o b e divide d do w n t o p r o d uce t h e r e fer e n c e clo c k t o t h e phas e f r eq uen c y det e c t o r (p fd). di vis i o n ra tios f r o m 1 t o 16,383 a r e allo w e d . pf d an d c h arge pump the p f d t a k e s i n p u ts f r o m t h e r co un t e r and n co un t e r ( n = bp + a ) a n d pro d u c e s a n output prop or t i on a l to t h e ph a s e a nd f r e q uen c y dif f er en ce b e twe e n t h e m . f i gur e 12 is a sim p li - f i e d s c h e ma t i c. the p f d i n cl u d es a p r og ra mma b l e dela y e l e - m e n t tha t co n t r o ls th e wi d t h o f th e a n t i ba ckla s h p u lse . t h i s p u ls e en s u r e s t h a t t h er e is n o de ad zon e i n t h e pfd t r a n sfer f u n c t i on an d m i nim i zes phas e n o is e an d r e fer e n c e sp urs. t w o b i ts in t h e r coun t e r l a t c h, abp2 a nd ab p1, c o n t r o l t h e wi d t h o f t h e p u ls e (s e e t a b l e 9). 04437-012 programmable delay u3 clr2 q2 d2 u2 clr1 q1 d1 charge pump down up hi hi u1 abp1 abp2 r divider n divider c p output r divider n divider cp cpgnd v p f i gur e 1 2 . p f d simpl i f ie d s c hema ti c and t i mi ng (in l o c k )
adf4360-3 rev. b | page 10 of 24 muxout a n d loc k de tect the o u t p u t m u l t i p lexer o n th e ad f4360 fa mily al lo ws th e us er t o acces s va r i o u s in t e r n al p o in ts o n t h e chi p . the s t a t e o f mux o ut is con t r o l l ed b y m3, m2, a nd m1 in t h e f u n c tion l a tc h . t h e f u l l t r ut h t a bl e i s s h ow n on t a bl e 7 . f i g u re 1 3 show s t h e m u x o u t s e c t io n i n b l o c k di a g r a m fo r m . lock det e ct mux o ut can be p r ogra mm e d f o r tw o types o f lo c k d e t e ct: dig i t a l an d analog. dig i tal lo ck det e c t is ac t i v e hig h . w h en ldp in t h e r co u n t e r la t c h is s et t o 0, dig i t a l lo ck de te c t is s et hig h w h en t h e phas e er r o r o n t h r e e co n s e c u t i v e phas e det e c t o r c y cles is les s tha n 15 ns. w i t h ld p s e t t o 1, f i v e co n s ec u t i v e c y c l es o f les s tha n 15 n s phas e er r o r a r e r e q u ir e d t o s e t t h e lo ck dete c t . i t wi l l s t a y s e t h i gh un til a p h ase e r r o r o f g r ea t e r th a n 25 n s i s d e t e ct e d o n a n y subs e q u e n t pd c y cl e. the n-c h a n ne l o p en-dra in a n al og lo c k det e c t sh o u ld be op er- a t e d w i t h an e x t e r n a l pu l l - u p re s i stor of 1 0 k ? nom i n a l. whe n lo c k has been det e c t e d , this o u t p u t wil l b e hig h wi t h na r r o w lo w-g o in g p u ls es. r counter output n counter output digital lock detect dgnd control mux muxout dv dd analog lock detect sdout 04437-013 f i g u re 13. m u x o u t ci r c u i t inpu t shift register the ad f4360 f a mil y s dig i tal s e c t io n in c l udes a 24-b i t in p u t s h if t r e g i st er , a 14-b i t r co u n t e r , a nd an 18-b i t n co un t e r , co m p r i s e d o f a 5-b i t a co un ter a nd a 13 -b i t b c o un t e r . d a t a is c l oc k e d in t o th e 24- b i t s h i f t r e gis t e r o n ea ch ri s i n g ed g e o f c l k . the da t a is c l o c k e d in ms b f i r s t. da t a is tra n sf er r e d f r o m th e s h if t r e g i st er t o o n e o f fo ur la t c h e s on t h e r i sin g e d g e o f le. th e des t ina t io n la t c h is det e r m i n e d b y t h e s t a t e o f t h e tw o co n t r o l b i ts (c2, c1) in t h e shif t r e g i st er . th es e a r e t h e t w o ls bsd b1, d b 0as sh o w n in f i gur e 2. the t r u t h t a b l e fo r t h es e b i ts is s h own i n t a b l e 5. t a b l e 6 s h o w s a s u mma r y o f ho w t h e l a t c h e s ar e p r og ra mm e d . n o t e t h a t t h e te st mo d e l a tch i s u s e d for f a c t or y te st i n g and s h ou l d not b e p r ogra m m e d b y th e user . table 5. c2 an d c1 truth ta ble control bits c2 c1 data latch 0 0 control latch 0 1 r counter 1 0 n counter (a an d b) 1 1 test mode latc h vco the v c o co r e in the ad f4360 fa mil y us es eig h t o v erla p p i n g ba nds, as sh o w n in f i gur e 14, t o al lo w a wide f r eq uen c y ra n g e t o b e c o ve re d w i t h out a l a r g e v c o s e ns it i v it y ( k v ) a nd r e su l t an t p o o r phas e n o is e a nd s p ur io us p e r f o r ma n c e . t h e co rr ect ba n d i s c h osen a u t o m a ti call y b y th e ba n d s e lect log i c a t p o w e r - up o r w h e n e v er t h e n co un t e r l a tch is u p da t e d . i t i s i m po r t a n t tha t th e co rr ect w r i t e seq u en ce b e f o llo w ed a t p o w e r - u p . this s e q u e n ce is 1. r c o u n te r l a tc h 2. c o n t r o l la t c h 3. n c o u n te r l a tch dur i n g ba nd s e lec t log i c, whic h tak e s f i ve p f d c y c l es, th e v c o v tun e i s d i s c on ne c t e d f rom t h e output of t h e l o op f i lte r an d co nne c t e d to an in ter n a l r e fer e nce vol t a g e. 04437-014 0.7 0.5 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.7 2.5 2.3 2.9 3.1 3.3 2050 1950 1850 1750 1650 1550 1450 1350 frequency (mhz) voltage (v) fi g u r e 1 4 . fr e q u e n c y v s . v tu ne , a d f4 3 60- 3 th e r co un t e r o u t p u t is us e d as th e clo c k fo r t h e b a n d s e le c t log i c a n d s h o u ld n o t e x ce e d 1 mh z. a p r ogra mma b l e d i vider i s p r o v ided a t th e r co un t e r in p u t t o all o w di visio n b y 1, 2 , 4, o r 8 a n d is co n - t r o lle d b y b i ts b s c1 a n d bsc2 in t h e r co un t e r la t c h. w h er e t h e r e q u i r ed p f d f r e q ue n c y e x ce ed s 1 mh z , th e d i v i d e ra ti o s h o u ld be s et t o allo w en o u g h t i m e f o r co rr ec t b a n d s e lec t io n . a f ter b a nd s e l e c t , no r m a l pl l a c t i on r e su me s. t h e nom i n a l va lu e of k v is 45 mh z/v o r 23 mh z/v if di vide-b y- 2 o p era t io n has bee n s e l e c t e d ( b y p r o g r a mming di v2 [db 2 2] hig h in t h e n c o u n ter la t c h). th e ad f4360 fa mil y co n t a i n s lin e a r iza t io n cir c ui tr y t o minimize a n y va r i a t io n o f t h e p r o d uc t o f i cp and k v .
adf4360-3 rev. b | page 11 of 24 the o p er a t in g c u r r en t in t h e v c o co r e is p r og ra mma b l e i n fo ur s t eps: 5 ma, 10 ma, 15 ma, and 20 ma. this is co n t r o l l ed b y b i ts pc1 and p c 2 in t h e con t rol la t c h. outpu t st age the rf ou t a and rf ou t b p i n s of th e ad f4360 f a mil y a r e co n- n e ct ed t o th e collect o r s o f a n np n di f f e r e n ti al pa i r d r i v e n b y b u f f er ed o u t p u t s o f th e v c o , as s h o w n in f i gur e 15. t o al lo w t h e us er t o o p t i mi ze t h e p o w e r dis s i p a t io n vs. t h e o u t p ut p o w e r r e q u ir em e n ts, t h e t a i l c u r r en t of t h e dif f er en t i al p a ir is p r o- g r a mma b l e vi a b i ts p l 1 and p l 2 in t h e con t r o l la t c h. f o ur c u r r en t lev e ls ma y be s et: 3.5 ma, 5 ma, 7.5 ma, a nd 11 ma. th es e leve ls g i ve o u t p u t p o w e r lev e ls o f ?12 db m, ?9 db m, ?6 dbm, an d ?3 dbm, r e sp e c t i vely , usin g a 50 ? r e sisto r to v dd a nd ac co u p li n g in to a 50 ? lo ad . a l ter n a t i v ely , b o t h o u t p u t s c a n be com b in e d in a 1 + 1:1 tra n sf o r m e r o r a 180 micr os tr i p co u - p l e r (see th e ou t p u t m a t c h i n g s e cti o n ) . i f th e o u t p u t s a r e used in di v i d u all y , th e o p tim u m o u t p u t s t a g e co n s is ts o f a sh un t i n d u c t o r t o v dd . an o t h e r fe a t ur e o f t h e ad f4360 fa mi l y i s tha t t h e s u p p l y c u rr en t t o th e r f o u t p u t s t a g e i s s h u t d o w n un til th e pa r t a c h i ev e s loc k a s m e a s ur ed b y th e d i gi tal loc k d e t e ct ci r c ui t r y . t h i s i s e n a b led b y th e m u te - t i l l - l o ck dete c t (m tl d ) b i t i n t h e c o n t rol l a tch. vco rf out ar f out b buf f e r/ di v i de by 2 04437-015 f i g u re 15. o u t p ut s t ag e a d f4 3 60- 3
adf4360-3 rev. b | page 12 of 24 latch structure t a b l e 6 sh o w s th e thr e e on-chi p la t c h e s f o r the ad f4360 fa mily . th e tw o ls bs decide which la t c h is p r og ra mm e d . table 6. latch structure db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) pc1 pc2 cr m1 m2 pdp cp cpg mtld pl1 pl2 cpi1 cpi2 cpi3 cpi4 cpi5 cpi6 pd1 m3 c o nt ro l bi t s mux o u t c o nt ro l curr e n t se t t in g 2 curr e n t se t t in g 1 pr es c a l er va l u e core power level output power level db21 db22 db23 power- down 2 power- down 1 counter reset mute-till- ld cp gain cp t hree- st at e phase det e ct or pol arit y pd2 p1 p2 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) r1 r2 r3 r4 r5 r7 r8 r9 r10 r11 r12 r13 r14 abp1 abp2 ldp tmb bsc1 r6 c o nt ro l bi t s b and se l e c t cl o c k ant i - back la s h pu l s e wi dt h 14-bit reference counter db21 db22 db23 loc k det e ct precision t est mode bit reserved reserved divide- by- 2 divide- b y- 2 select bsc2 rsv rsv db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 rsv c o nt ro l bi t s 5-bit a counter 13-bit b counter control latch n counter latch r counter latch db21 db22 db23 cp gain reserved cpg div2 divsel 04437-016
adf4360-3 rev. b | page 13 of 24 table 7. co ntrol latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) pc1 pc2 cr m1 m2 pdp cp cpg mtld pl1 pl2 cpi1 cpi2 cpi3 cpi4 cpi5 cpi6 pd1 m3 co ntro l bi ts mu x o ut co ntro l c urre n t s e tti n g 2 c urre n t s e tti n g 1 pr e s c a l er va l u e core power level output power level db21 db22 db23 power- down 2 power- down 1 count er reset mu te - t i ll- ld cp gain cp t hree- state phase det e ct o r po l arit y pd2 p1 p2 cr 0 1 counter operation normal r, a, b counters held in reset pc2 0 0 10 c o r e po w e r l evel 5m a 10m a 15m a pc1 0 1 11 20m a cp 0 1 charge pump output normal three-state pdp 0 1 phase detector polarity ne g a t i v e po si t i v e cpg 0 1 cp gain curre nt s e t t i n g 1 curre nt s e t t i n g 2 mtld 0 1 mute-till-lock detect di s abl e d e nabl e d m3 m2 m1 ou tp u t three-state output 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 digital lock detect (active high) n divider output dv dd r divider output n-channel open-drain lock detect s e r i a l dat a o ut p u t dgnd p2 p1 prescaler value 0 0 8/9 0 1 16/17 1 0 32/33 1 1 32/33 ce pin pd2 pd1 mode 0 x x asynchronous power-down 1 x 0 normal operation 1 0 1 asynchronous power-down 1 1 1 synchronous power-down cpi6 cpi5 cpi4 i cp (ma) cpi3 cpi2 cpi1 4.7k ? 0.31 0.62 0.93 1.25 1.56 1.87 2.18 2.50 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 pl2 pl1 output power level current power into 50 ? (using 50 ? to v cc ) ?1 2 dbm ?9 dbm ?6 dbm ?3 dbm 0 0 1 1 0 1 0 1 3.5ma 5.0ma 7.5ma 11.0ma 04437-017
adf4360-3 rev. b | page 14 of 24 tab l e 8. n cou n ter latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) a1 a2 a3 a4 a5 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 rsv co ntro l bi t s 5-bit a counter 13-bit b counter db21 db22 db23 cp gain divide-by- 2 select divide- by-2 reserved cpg div2 divsel this bit is not used by the device and is a don't care bit. a5 a4 .......... a2 a1 a counter divide ratio 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 2 8 1 1 .......... 0 1 2 9 1 1 .......... 1 0 3 0 1 1 .......... 1 1 3 1 f4 (function latch) fastlock enable cp gain operation charge pump current setting 1 is permanently used 0 0 charge pump current setting 2 is permanently used 1 0 n = bp + a; p is prescaler value set in the control latch. b must be greater than or equal to a. for continuously adjacent values of (n f ref ), at the output, n min is (p 2 ? p). b13 b12 b11 b3 b2 b1 b counter divide ratio .......... 0 00 0 00 0 00 0 00 0 0 0 not allowed .......... 0 0 1 not allowed .......... 0 1 0 not allowed .......... 1 1 1 3 .......... . .. . .. . .. . .. . .......... . . . . .......... . . . . .......... 1 11 1 11 1 11 1 11 1 0 0 8188 .......... 1 0 1 8189 .......... 1 1 0 8190 .......... 1 1 1 8191 04437-018 div2 0 1 divide-by-2 f unda m e nt al o u t p ut divide-by-2 divsel 0 1 divide-by-2 select (prescaler input) f u nd a m ent a l o u t pu t s el ect e d divide-by-2 s e l e c t e d
adf4360-3 rev. b | page 15 of 24 tab l e 9. r cou n ter latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) r1 r2 r3 r4 r5 r7 r8 r9 r10 r11 r12 r13 r14 abp1 abp2 ldp tmb bsc1 r6 co n t ro l bi t s ba nd se l e c t clo c k an t i - ba ck las h pu l s e wi d t h 14-bit reference counter db21 db22 db23 lo ck detect precision test mode bit reserved reserved bsc2 rsv rsv test mode bit should be set to 0 for normal operation. r14 r13 r12 r3 r2 r1 divide ratio .......... 0 00 0 00 0 00 0 00 0 00 1 .......... 0 1 1 2 .......... 0 1 0 3 .......... 1 0 1 4 .......... . .. . .. . .. . .. . .......... . . . . .......... . . . . .......... 1 11 1 11 1 11 1 11 1 0 0 16380 .......... 1 0 1 16381 .......... 1 1 0 16382 .......... 1 1 1 16383 these bits are not used by the device and are don't care bits. 04437- 019 ldp lock detect precision 0 three consecutive cycles of phase delay less than 15ns must occur before lock detect is set. 1 five consecutive cycles of phase delay less than 15ns must occur before lock detect is set. abp2 abp1 antibacklash pulse width 0 0 3.0ns 0 1 1.3ns 1 0 6.0ns 1 1 3.0ns bsc2 bsc1 band select clock divider 00 1 01 2 10 4 11 8
adf4360-3 rev. b | page 16 of 24 power-up power-up s e q u en ce the co r r ec t p r og ra mmin g s e q u en c e f o r th e adf4360-3 a f t e r po w e r - u p i s : 1. r c o u n te r l a tc h 2. c o n t r o l la t c h 3. n c o u n te r l a tch initial power-up i n i t ial p o w e r - u p r e f e r s t o p r ogr a mmin g the p a r t a f t e r the ap p l i c at i o n o f v o l t a g e t o t h e a v dd , d v dd , v vc o , a n d c e p i n s . o n ini t ia l p o w e r - u p , a n in t e r v a l is r e q u ir e d b e tw e e n p r og ra mmin g th e co n t r o l la t c h an d p r ogra mm in g t h e n co un t e r la t c h . t h i s in t e r v al i s n e ces s a r y t o allo w th e tra n s i en t be ha v i o r o f th e ad f4360-3 d u r i n g ini t ial p o w e r - u p t o ha ve s e t t led . dur i n g i n i t i a l po w e r - u p , a w r i t e t o th e co n t r o l l a t c h po w e r s u p th e pa r t , a nd t h e b i as c u r r en ts o f t h e v c o b e g i n s t o s e t t le . i f t h es e c u r - r e n t s ha ve n o t s e t t le d t o w i t h i n 10% o f t h eir st e a d y -s t a te val u e , a n d i f th e n co un t e r la t c h i s th en p r ogra m m e d , th e v c o ma y n o t b e ab le t o os ci l l a t e a t t h e de sir e d f r e q uen c y , w h ich do es n o t al lo w th e band s e lec t log i c t o c h o o s e t h e co r r e c t f r eq uen c y ba nd , and the ad f4360-3 ma y n o t achie v e lo c k . i f th e r e co m- m e n d ed in t e r v a l i s i n se r t ed , a n d th e n co un t e r la t c h i s p r o- g r a m m e d , t h e b a nd s e lec t log i c ca n ch o o s e t h e co r r ec t f r e- q u en c y b a nd , and t h e p a r t lo cks t o t h e co r r e c t f r e q uen c y . t h e d u ra ti o n o f th i s i n t e r v al i s a f f e ct ed b y th e v a l u e o f th e ca - pa c i t o r o n th e c n p i n (p in 14). this c a p a ci t o r is us ed t o r e d u ce th e c l os e-in n o is e o f th e ad f4360-3 v c o . the r e co mmen d e d va l u e o f t h is ca p a ci t o r is 10 f . u s in g t h is va l u e r e q u ir es a n i n - t e r v al o f 5 m s b e tw e e n t h e l a tchin g i n o f t h e c o n t r o l la t c h b i ts and l a tch i ng i n of t h e n c o u n te r l a tc h bi t s . i f a shor te r de l a y i s r e q u ir e d , t h is c a p a ci t o r can b e r e d u ce d . a slig h t phas e n o is e p e na lty is in c u r r e d b y t h is cha n ge , w h ich is expla i n e d f u r t h e r in t a b l e 10. table 10. c n c a pacitance vs. i n terval a n d phase noise c n va lue recommended interval betwe e n control latch and n count e r latch op en-loop phase noise @ 10 khz offset 10 f 5 ms ?87 dbc 440 nf 600 s ?86 dbc clock power-up data le r counter latch data control latch data n counter latch data required interval control latch write to n counter latch write 04437-020 f i g u re 16. a d f4 36 0-3 p o wer - u p ti mi ng
adf4360-3 rev. b | page 17 of 24 hardware power-up/power-down if the part is powered down via the hardware (using the ce pin) and powered up again without any change to the n counter register during power-down, the part locks at the correct fre- quency because the part is already in the correct frequency band. the lock time depends on the value of capacitance on the c n pin, which is <5 ms for 10 f capacitance. the smaller ca- pacitance of 440 nf on this pin enables lock times of <600 s. the n counter value cannot be changed while the part is in power-down, since the part may not lock to the correct fre- quency on power-up. if it is updated, the correct programming sequence for the part after power-up is to the r counter latch, followed by the control latch, and finally the n counter latch, with the required interval between the control latch and n counter latch, as described in the initial power-up section. software power-up/power-down if the part is powered down via the software (using the control latch) and powered up again without any change to the n counter latch during power-down, the part locks at the correct frequency because the part is already in the correct frequency band. the lock time depends on the value of capacitance on the c n pin, which is <5 ms for 10 f capacitance. the smaller ca- pacitance of 440 nf on this pin enables lock times of <600 s. the n counter value cannot be changed while the part is in power-down because the part may not lock to the correct fre- quency on power-up. if it is updated, the correct programming sequence for the parts after power-up is to the r counter latch, followed by the control latch, and finally the n counter latch, with the required interval between the control latch and n counter latch, as described in the initial power-up section.
adf4360-3 rev. b | page 18 of 24 control latch with (c2, c1) = (0, 0), the control latch is programmed. table 7 shows the input data format for programming the control latch. prescaler value in the adf4360 family, p2 and p1 in the control latch set the prescaler values. power-down db21 (pd2) and db20 (pd1) provide programmable power- down modes. in the programmed asynchronous power-down, the device powers down immediately after latching a 1 into bit pd1, with the condition that pd2 has been loaded with a 0. in the pro- grammed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. once the power-down is enabled by writing a 1 into bit pd1 (on the condition that a 1 has also been loaded to pd2), the device will go into power-down on the second rising edge of the r counter output, after le goes high. when the ce pin is low, the device is immediately disabled regardless of the state of pd1 or pd2. when a power-down is activated (either synchronous or asynchronous mode), the following events occur: ? all active dc current paths are removed. ? the r, n, and timeout counters are forced to their load state conditions. ? the charge pump is forced into three-state mode. ? the digital lock detect circuitry is reset. ? the rf outputs are debiased to a high impedance state. ? the reference input buffer circuitry is disabled. ? the input register remains active and capable of loading and latching data. charge pump currents cpi3, cpi2, and cpi1 in the adf4360 family determine current setting 1. cpi6, cpi5, and cpi4 determine current setting 2. see the truth table in table 7. output power level bits pl1 and pl2 set the output power level of the vco. see the truth table in table 7. mute-till-lock detect db11 of the control latch in the adf4360 family is the mute-till- lock detect bit. this function, when enabled, ensures that the rf outputs are not switched on until the pll is locked. cp gain db10 of the control latch in the adf4360 family is the charge pump gain bit. when it is programmed to a 1, current setting 2 is used. when it is programmed to a 0, current setting 1 is used. charge pump three-state this bit puts the charge pump into three-state mode when programmed to a 1. it should be set to 0 for normal operation. phase detector polarity the pdp bit in the adf4360 family sets the phase detector polarity. the positive setting enabled by programming a 1 is used when using the on-chip vco with a passive loop filter or with an active noninverting filter. it can also be set to 0. this is required if an active inverting loop filter is used. muxout control the on-chip multiplexer is controlled by m3, m2, and m1. see the truth table in table 7. counter reset db4 is the counter reset bit for the adf4360 family. when this is 1, the r counter and the a, b counters are reset. for normal operation, this bit should be 0. core power level pc1 and pc2 set the power level in the vco core. the recom- mended setting is 15 ma. see the truth table in table 7.
adf4360-3 rev. b | page 19 of 24 n counter latch with (c2, c1) = (1, 0), the n counter latch is programmed. table 8 shows the input data format for programming the n counter latch. a counter latch a5 to a1 program the 5-bit a counter. the divide range is 0 (00000) to 31 (11111). reserved bits db7 is a spare bit that is reserved. it should be programmed to 0. b counter latch b13 to b1 program the b counter. the divide range is 3 (00.....0011) to 8191 (11....111). overall divide range the overall divide range is defined by ((p b) + a), where p is the prescaler value. cp gain db21 of the n counter latch in the adf4360 family is the charge pump gain bit. when this is programmed to 1, current setting 2 is used. when programmed to 0, current setting 1 is used. this bit can also be programmed through db10 of the control latch. the bit will always reflect the latest value written to it, whether this is through the control latch or the n counter latch. divide-by-2 db22 is the divide-by-2 bit. when set to 1, the output divide-by-2 function is chosen. when it is set to 0, normal operation occurs. divide-by-2 select db23 is the divide-by-2 select bit. when programmed to 1, the divide-by-2 output is selected as the prescaler input. when set to 0, the fundamental is used as the prescaler input. for exam- ple, using the output divide-by-2 feature and a pfd frequency of 200 khz, the user will need a value of n = 8,000 to generate 800 mhz. with the divide-by-2 select bit high, the user may keep n = 4,000. r counter latch with (c2, c1) = (0, 1), the r counter latch is programmed. table 9 shows the input data format for programming the r counter latch. r counter r1 to r14 set the counter divide ratio. the divide range is 1 (00......001) to 16383 (111......111). antibacklash pulse width db16 and db17 set the antibacklash pulse width. lock detect precision db18 is the lock detect precision bit and sets the number of reference cycles with less than 15 ns phase error for entering the locked state. with ldp at 1, five cycles are taken; with ldp at 0, three cycles are taken. test mode bit db19 is the test mode bit (tmb) and should be set to 0. with tmb = 0, the contents of the test mode latch are ignored and normal operation occurs as determined by the contents of the control latch, r counter latch, and n counter latch. note that test modes are for factory testing only and should not be pro- grammed by the user. band select clock these bits set a divider for the band select logic clock input. the output of the r counter is by default the value used to clock the band select logic, but if this value is too high (>1 mhz), a divider can be switched on to divide the r counter output to a smaller value (see table 9). reserved bits db23 to db22 are spare bits that are reserved. they should be programmed to 0.
adf4360-3 rev. b | page 20 of 24 appli c ations direct c o n v ersion m o dulat o r d i re c t c o n v e r s i on arch ite c tu re s are i n c r e a s i ng l y b e i n g u s e d to i m p l em en t base s t a t i o n tra n s m i t t e r s . f i g u r e 17 s h o w s h o w a d i p a r t s ca n b e us e d t o im plemen t s u ch a sys tem. the cir c ui t b l o c k dia g ram sh o w s th e ad9761 txd a c? bein g us ed wi t h the ad8349. the us e o f d u al in t e g r a t ed d a cs, s u c h as the ad9761 wi t h i t s s p ecif ie d 0.02 db and 0.004 db ga in a nd o f fs et ma tchin g cha r ac ter is t i cs, en s u r e s mi nim u m er r o r c o n t r i but i on ( o ve r te m p e r atu r e ) f rom t h i s p o r t i o n of t h e sig n al c h a i n. the lo cal os cil l a t o r is im p l em en t e d usin g t h e ad f4360-3. th e lo w-p a ss f i l t er was desig n e d usin g adi s i m pll fo r a cha nnel s p acin g o f 100 kh z an d a n op en-lo o p bandwid th o f 10 kh z. the f r eq uen c y r a n g e o f th e adf4360-3 (1.6 gh z t o 1.95 gh z) m a k e s i t i d eall y s u i t e d f o r i m p l em en t a ti o n o f a w - cd ma tra n sce i v e r . the l o p o r t s o f th e ad8349 c a n b e dr i v en dif f er en tial l y f r o m th e co m p lem e n t a r y r f ou t a and rf ou t b output s of t h e ad f4360-3. this g i v e s a bet t e r p e r f o r ma n c e tha n a sin g le- en d e d lo dr i v e r a n d elim ina t es t h e o f te n n e ce ss a r y us e o f a bal u n t o co n v e r t f r o m a s i n g le -e n d ed l o i n p u t t o th e m o r e desira b l e dif f er en tial l o in p u ts f o r th e ad8349. the typ i cal r m s p h as e n o is e (100 h z t o 100 kh z) o f th e lo in this co nf igura t io n is 1.17. the ad8349 ac cep t s l o dr i v e lev e ls f r o m ?10 db m t o 0 db m. t h e o p tim u m lo po w e r ca n be so f t wa r e p r ogra mm ed o n t h e ad f4360-3, whic h al lo ws lev e ls f r o m ?12 db m t o ?3 db m f r o m ea c h o u t p u t . the rf o u t p u t i s desig n e d t o dr i v e a 50 ? lo ad b u t m u s t b e ac- co u p le d , as sh ow n in f i gur e 17. i f t h e i and q i n p u ts a r e dr i v e n i n q u a d r a tu re by 2 v p - p s i g n a l s , t h e re su lt i n g output p o we r f r o m th e m o d u la t o r w i ll be a p p r o x i m a t e l y 2 d b m ad9761 txdac ad8349 refio fsadj modulated digital data qoutb iouta ioutb qouta 2k ? low-pass filter low-pass filter s p i comp atible s e r ial bus adf4360-3 v vco v vco v vco cpgnd agnd dgnd rf out b rf out a cp 1nf 470pf 220pf 6.8nf 47nh 47nh 2.7pf 2.7pf 100pf to rf pa 4.3nh 4.3nh 1nf 1nf 4.7k ? 15k ? 6.8k ? r set c c le data clk ref in fref in c n v tune dv dd av dd ce muxout vps1 ibbp ibbn qbbp qbbn loip loin vps2 5 4 24 7 20 23 2 21 6 14 16 17 18 19 13 1 3 8 9 10 11 22 15 12 v dd lock detect phase splitter 04437-021 51 ? 10 f f i g u re 17. d i r e c t convers i on m o du l a t o r
adf4360-3 rev. b | page 21 of 24 fixe d freq uency l o f i gur e 18 s h o w s th e ad f4360-3 us ed as a f i xe d f r eq uen c y l o a t 1.8 gh z. th e lo w-p a s s f i l t er was desig n e d using ad i s imp l l f o r a cha n nel sp aci n g o f 8 mh z and a n op en -lo o p b a ndwi d t h o f 40 kh z. th e maxim u m p f d f r eq uen c y o f th e ad f4360-3 is 8 mh z. b e ca us e usin g a la rg er pfd f r eq uen c y al lo ws us ers t o us e a smal ler n, t h e i n -b an d phas e n o is e is r e d u ce d t o as lo w as p o s s i b l e , C99 db c/h z . th e 40 kh z b a n d wid t h is c h os en t o b e j u s t gr ea t e r th a n th e po in t a t w h i c h t h e o p en - l oo p p h a s e n o i s e o f t h e v c o is C 99 db c/ h z , t h us g i vi n g t h e b e s t p o s s i b le i n te- g r a t ed n o is e . the typ i c a l r m s p h as e n o is e (100 h z t o 100 kh z) o f t h e lo i n t h i s co nf igura t io n is 0.3. the r e fer e n c e f r e q uen c y i s f rom a 1 6 m h z tc x o f rom f o x ; t h u s an r v a lu e of 2 i s pro - g r a m m e d . t a ki n g in t o acco un t t h e hig h p f d f r e q uen c y and i t s ef fe c t o n t h e b a nd s e le c t lo g i c, t h e b a n d s e le c t clo c k divider is ena b le d . i n t h is cas e , a val u e o f 8 is ch os en. a ver y sim p le p u l l - up re s i stor an d d c bl o c k i ng c a p a c i tor c o m p l e te t h e r f output st age . s p i com p atible s e r ial bus adf4360-3 v vco v vco fox 801be-160 16mhz v vco cpgnd agnd dgnd rf out b rf out a cp 1nf 3.9nf 22.0nf 51 ? 51 ? 51 ? 100pf 100pf 1nf 1nf 10 f 4.7k ? 470 ? r set c c le data clk ref in c n v tune dv dd av dd ce muxout 5 4 24 7 20 23 2 21 6 14 16 17 18 19 13 1 3 8 9 10 11 22 15 12 v vdd lock detect 04437- 022 fi g u r e 1 8 . fi x e d fr e q u e n c y l o interfacing the ad f4360 f a mil y has a sim p le s p i?-com p a t i b l e s e r i al in t e r - face f o r wr i t in g t o th e de vice . clk, d a t a , and le co n t r o l th e da ta tra n s f e r . w h en l e g o e s h i g h , th e 24 b i t s tha t ha v e been cl o c ke d i n to t h e a ppropr i a t e re g i ste r on e a c h r i s i ng e d g e of c l k wi l l g et t r an sfer r e d t o t h e a p p r o p r i a te l a t c h. s e e f i gur e 2 fo r t h e ti m i n g di a g ra m a n d t a b l e 5 f o r th e la t c h tr u t h t a b l e . the max i m u m a l lo wa ble s e r i a l clo c k r a te is 20 mh z. t h is m e an s t h e maxi m u m up da t e ra te p o s s i b le is 833 kh z o r o n e u p da te e v er y 1.2 s. this is cer t a i nly m o r e t h a n ade q u a te fo r sys t em s t h a t wil l ha v e typ i cal lo c k t i m e s in h u ndr e d s o f micr o- sec o n d s . aduc812 interface f i gur e 19 s h o w s th e in t e r f ace betw een t h e ad f 4360 fa mil y an d th e aduc812 m i cr oc o n v e r t er? b e ca us e t h e aduc812 is bas e d o n a n 8051 co r e , this in t e r f ace c a n be us ed wi th a n y 8051 bas e d micr o c o n t r ol ler . the micr oc o n v e r t er is s et u p fo r s p i mas ter m o de wi t h cph a = 0. t o ini t i a t e t h e op era t ion, t h e i / o p o r t dr i v in g le is b r o u g h t lo w . e a c h la t c h o f th e adf4360 fa mil y ne e d s a 2 4 - bit word, w h i c h i s a c c o m p l i s h e d by w r it i n g t h re e 8-b i t b y t e s f r o m t h e micr oc on ver t er t o t h e de v i ce . w h en t h e t h ir d b y t e has b e en wr i t t e n, t h e le in p u t sh o u ld b e b r o u g h t hig h t o com p lete t h e t r an sfer . 04437-023 aduc812 adf4360-x sclk sdata le ce muxout (lock detect) sclock mosi i/o ports f i g u re 19. a d uc8 1 2 t o a d f4 3 60-x i n t e r f ace i/o p o r t lin e s o n the adu c 812 a r e als o us ed t o co n t r o l p o w e r - do wn ( c e i n p u t ) a nd dete c t lo ck ( m u x ou t c o nf igur e d as lo ck det e c t and p o l l e d b y t h e p o r t in p u t). w h en o p e r a t in g i n t h e des c r i b e d m o de, th e maxim u m scl o ck ra te of th e adu c 812 is 4 mh z. this m e an s t h a t t h e maxim u m ra te a t w h ich t h e ou t - p u t f r eq uen c y c a n be c h an g e d is 166 kh z. adsp-2181 interface f i gur e 20 s h o w s th e in t e r f ace betw een t h e ad f 4360 fa mil y an d th e ads p -21xx dig i t a l sig n al p r o c es s o r . the ad f4360 fa mil y n e e d s a 24- b i t s e r i al w o r d fo r e a ch l a t c h wr i t e . the e a siest wa y t o acco m p lish t h is usin g t h e a d s p -21xx fa mi ly is t o us e t h e a u t o b u f f er e d t r an smi t m o de o f o p era t ion wi t h al t e r n a te f r a m - i n g . t h i s prov i d e s a m e ans f o r t r ans m itt i ng an e n t i re bl o c k of se ri al d a ta be f o r e a n in t e rr u p t i s g e n e ra t e d . 04437-024 adsp-21xx adf4360-x sclk sdata le ce muxout (lock detect) sclock mosi tfs i/o ports f i g u re 20. a d s p -2 1 x x to a d f4 3 60-x i n ter f a c e s et u p t h e w o r d len g t h fo r 8 b i t s a nd us e t h r e e m e m o r y lo ca - t i ons f o r e a ch 2 4 - b it word. t o pro g r a m e a ch 2 4 - bit l a tc h , store t h e 8- b i t b y t e s, ena b le t h e a u t o b u f f er e d mo de , a nd wr i t e t o t h e tra n s m i t r e gis t er o f th e d s p . t h i s la s t o p e r a t i o n i n i t ia t e s t h e a u t o b u f f er t r a n sfer .
adf4360-3 rev. b | page 22 of 24 pcb desig n guidelines for chip sc ale packag e the le ads o n t h e chi p s c ale p a cka g e (c p - 24) a r e r e c t a n gu la r . the p r in te d cir c ui t b o a r d p a d for t h es e sh o u ld b e 0.1 mm lo n g e r th a n th e pa c k a g e lead len g th a n d 0. 05 m m w i d e r th a n t h e p a cka g e le ad w i d t h. th e le ad sh o u ld b e ce n t er e d on t h e p a d t o en s u r e t h a t t h e s o lder join t s i ze is maximize d . the b o t t o m o f t h e chi p s c ale p a cka g e has a ce n t ral t h er mal p a d . the t h er mal p a d o n t h e p r i n t e d cir c ui t b o a r d sh o u ld b e a t le ast as la rg e as t h is e x p o s e d p a d . o n t h e p r in t e d cir c ui t b o a r d , t h er e s h o u ld b e a cle a ra n c e o f a t le as t 0.25 mm b e tw e e n t h e t h er mal p a d an d t h e in ner e d ges o f t h e p a d p a t t er n to e n sur e t h a t sh o r t - in g is a v o i de d . ther mal v i as ma y b e us e d on t h e p r i n t e d cir c ui t b o a r d t h er mal p a d t o im p r o v e t h er mal p e r f o r ma nce o f t h e p a cka g e . i f vi as a r e used , th ey s h o u ld b e in co r p o r a t ed in th e th e r m a l pa d a t a 1.2 mm pi t c h g r id . th e v i a diamet er s h o u ld b e b etw e e n 0.3 mm a nd 0.33 m m , and t h e v i a b a r r el sh o u ld b e pla t e d wi t h 1 o u nce o f co p p er t o p l ug th e via . the us er s h o u ld co nne c t t h e p r i n t e d cir c ui t t h er mal p a d t o a g nd . this is i n t e r n a l ly co nne c t e d t o a g nd . outpu t ma tchi ng ther e a r e a n u m b er o f wa ys t o ma t c h t h e o u t p u t o f t h e ad f4360-3 f o r o p tim u m o p er a t io n; the m o s t b a sic is t o us e a 5 0 ? re s i stor to v vc o . a dc b y p a s s ca p a c i t o r o f 100 pf is co n- ne c t e d i n s e r i e s , a s s h ow n fi g u re 2 1 . b e c a u s e t h e re s i stor i s not f r eq ue n c y d e pen d en t , th i s p r o v i d e s a g o o d b r o a d b a n d ma t c h . t h e output p o we r i n t h i s c i rc u i t t y pi c a l l y g i ve s ? 3 d b m output p o w e r in to a 50 ? lo ad . 100pf 04437-025 rf out v vco 50 ? 51 ? f i g u re 21. si mpl e a d f43 6 0 -3 o u t p ut s t ag e a bet t er s o l u tio n is t o us e a sh u n t ind u c t o r (ac t in g as an rf cho k e) to v vc o . this g i v e s a b e t ter ma t c h an d t h er efo r e m o r e o u t p ut p o w e r . a ddi t i ona l ly , a s e r i es in d u c t o r is adde d a f ter t h e d c b y pa s s ca pa ci t o r t o p r o v i d e a r e so n a n t l c c i r c u i t . t h i s t u n e s t h e o s c i l l a tor output a n d prov i d e s a ppro x i m a t el y 1 0 d b a d d i - t i on a l re j e c t i o n of t h e s e c o n d h a r m on i c . t h e sh u n t i n d u c t or n e e d s t o b e a r e l a ti ve l y hig h va l u e (>40 nh). e x p e r i me n t s h a ve sho w n t h a t t h e c i rc u i t s h ow n i n fi g u re 2 2 p r o v ides a n exc e l l en t ma t c h t o 50 ? o v er t h e o p era t i n g ra n g e o f th e ad f4360-3. this g i v e s a p p r o x ima t e l y ?2 db m o u t p u t p o wer acr o s s th e f r eq uen c y ra n g e o f the ad f4360-3. b o th sin g le- en de d a r chi t e c t u r e s ca n b e exami n e d usin g t h e e v al - ad f4360-3eb1 eval u a tion bo a r d . 4.3nh 47nh 2.7pf 04437-026 rf out v vco 50 ? f i g u re 22. o p t i m u m a d f 4 3 60- 3 o u t p ut st ag e i f t h e us er do es n o t n e e d t h e dif f er en t i al o u t p ut s a v a i la b l e on th e ad f4360, th e us er ma y ei t h er t e r m ina te th e u n us ed o u t p u t o r co m b in e bo t h o u t p u t s usi n g a bal u n . th e ci r c ui t i n f i gur e 23 shows how b e st to c o mb i n e t h e ou t p ut s . 2.4nh 3.9nh 47nh 3.9nh 1.8pf 10pf 1.8pf 50 ? 2.4nh rf out a v vco rf out b 04437-027 f i g u re 23. ba lun f o r co mb ining a d f4 36 0-3 r f o u t p ut s the cir c ui t in f i gur e 23 is a l u m p ed-l a t t i ce-typ e l c bal u n. i t is desig n e d fo r a c e n t er f r e q ue n c y o f 1.8 gh z and o u t p u t s 3 . 0 d b m a t this f r eq uen c y . th e s e r i es 2.4 nh ind u c t o r is us ed t o t u n e o u t a n y p a rasi t i c ca p a ci t a n c e d u e to t h e b o a r d l a yo u t f r o m e a ch in p u t, an d t h e rema i n der o f t h e cir c ui t is us e d to s h if t t h e o u t p u t o f o n e rf in p u t b y +90 a nd t h e s e cond b y ?90, th us co m b inin g t h e t w o . the ac t i o n o f t h e 3.9 nh i n d u c t o r an d t h e 1.8 pf ca p a ci t o r acco m p lish this . th e 47 nh is u s ed t o p r o v ide a n rf ch ok e i n o r d er t o fe e d t h e s u p p ly v o l t a g e, a n d t h e 10 pf c a p a c i tor prov i d e s t h e n e c e ss ar y d c bl o c k . t o e n su re go o d r f p e r f or m a nc e, t h e c i rc u i t s i n f i g u re 2 2 an d f i g u re 2 3 we re im p l em en t e d wi th c o ilcra f t 0402/0603 in d u c t o r s a nd a v x 0402 th i n - f ilm ca pa c i t o r s . a l ter n a t i v ely , inste a d o f t h e lc b a l u n sh o w n i n f i gur e 23, b o t h o u t p u t s ma y be co m b in e d usin g a 180 ra t-race co u p ler .
adf4360-3 rev. b | page 23 of 24 outline dimensions * compliant to jedec standards mo-220-vggd-2 except for exposed pad dimension 1 24 6 7 13 19 18 12 * 2.45 2.30 sq 2.15 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indicator top view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.23 min exposed pa d (bo tt om view) f i gure 24. 2 4 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e [ v q_ lfcsp ] 4 mm 4 m m b o d y , v e r y thin q u ad (cp - 24- 2) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge frequency r a nge package option adf4360-3bcp ?40c to +85c 1600 mhz to 19 50 mhz cp-24-2 adf4360-3bcprl ?40c to +85c 1600 mhz to 19 50 mhz cp-24-2 adf4360-3bcprl7 ?40c to +85c 1600 mhz to 19 50 mhz cp-24-2 adf4360-3bcpz 1 ?40c to +85c 1600 mhz to 19 50 mhz cp-24-2 ADF4360-3BCPZRL 1 ?40c to +85c 1600 mhz to 19 50 mhz cp-24-2 ADF4360-3BCPZRL7 1 ?40c to +85c 1600 mhz to 19 50 mhz cp-24-2 eval-adf4360- 3 e b 1 e v a l u a t i o n boar d 1 z = pb- f ree m o d e l.
adf4360-3 rev. b | page 24 of 24 notes purch a se of li c e n s e d i 2 c com p on en t s o f an a l og d e vi ces or on e of i t s subli c en s e d as soci a t ed c o m p a n i e s con v eys a li cen s e for t h e purch a ser un der t h e ph i li p s i 2 c p a te nt rights to us e the s e co mpo n e nts in an i 2 c sy st em , provi d e d t h a t t h e syst em c o n f orm s t o t h e i 2 c stand a rd speci f ication as d e f i ned by phil ips . ? 2004 a n alo g devic e s, inc. all rig h ts res e rve d . t r ade m arks a n d re g i s - tered trade m arks are the property of their respective owners . c04437C0 C 12/04(b)

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